IBM engineer: 14nm node will pose IC design challenges

04/2/2013 | EE Times Asia (free registration)

The 14-nanometer process node in semiconductor manufacturing will offer a number of technical challenges that cannot be addressed by simply scaling down from previous nodes, according to IBM's James Warnock. "The 14nm node poses a host of challenges for designers, because the solutions to problems with scaling have been postponed by previous generations," he said in a recently presented paper. "The end is nearish, and will eventually be determined by economic issues, but at 14nm there is no way to get more performance by scaling alone."

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